Selectable address translation mechanisms

ABSTRACT

An address translation capability is provided in which translation structures of different types are used to translate memory addresses from one format to another format. Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and the use of a particular translation structure format in translating an address is selectable.

This application is a continuation of co-pending U.S. Ser. No. 13/646,771, entitled “SELECTABLE ADDRESS TRANSLATION MECHANISMS,” filed Oct. 8, 2012, which is hereby incorporated herein by reference in its entirety.

BACKGROUND

One or more aspects relate, in general, to memory of a computing environment, and in particular, to facilitating translation of memory addresses used to access the memory.

System configurations include physical memory used to store applications and data. The amount of physical memory is fixed and often inadequate to support the needs of users. Therefore, to provide additional memory or at least the appearance of additional memory, a memory management technique, referred to as virtual memory, is utilized. Virtual memory uses virtual addressing, which provides ranges of addresses that can appear to be much larger than the physical size of main memory.

To access main memory in a system configuration that includes virtual memory, a memory access is requested that includes an effective address. The effective address is translated into a real address used to access the physical memory.

Translation is performed using an address translation technique. Several address translation techniques are available. For instance, in PowerPC systems offered by International Business Machines Corporation, an effective address is translated to a corresponding real address by way of page table entries found by selecting an effective segment identifier (ESID) table entry associated with the effective address, and using the entry to locate a group of page table entries by way of a hashing algorithm. In a further example, in the z/Architecture, also offered by International Business Machines Corporation, an effective address is translated to a corresponding real address by way of a hierarchy of translation tables. Translation tables are indexed by a portion of the effective address to find the address of the next translation table of the hierarchy until a real (or absolute) address is obtained. Both address translation techniques provide advantages to their respective operating systems.

BRIEF SUMMARY

Shortcomings of the prior art are overcome and additional advantages are provided through the provision of a method of facilitating translation of memory addresses. The method includes, for instance, obtaining, by a processor, a memory address to be translated, the processor having a first type of address translation structure and a second type of address translation structure available for translating the memory address, wherein the first type is structurally different from the second type; and selecting by the processor one type of address translation structure of the first type of address translation structure and the second type of address translation structure to be used in translating the memory address.

Computer program products and systems relating to one or more aspects are also described and may be claimed herein. Further, services relating to one or more aspects are also described and may be claimed herein.

Additional features and advantages are realized through the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the conclusion of the specification. The foregoing and objects, features, and advantages of one or more aspects are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:

FIG. 1A depicts one example of a computing environment to incorporate and use one or more aspects of a translation capability;

FIG. 1B depicts another example of a computing environment to incorporate and use one or more aspects of a translation capability;

FIG. 2A illustrates an example of a high-level view of a virtual memory mapped to a physical memory using a hash page table technique;

FIG. 2B illustrates one example of a technique for generating a virtual address;

FIG. 2C depicts one example of a hash page table translation structure;

FIG. 3 depicts one example of a segment lookaside buffer, including example fields of a segment lookaside buffer entry;

FIG. 4A depicts one example of a page table;

FIG. 4B depicts one example of a page table entry;

FIG. 5A depicts one example of a hierarchical translation mechanism;

FIG. 5B depicts one example of indexing of high-level translation tables;

FIG. 6A depicts an example of a page table entry for the z/Architecture;

FIG. 6B depicts one example of a page table entry for the Power ISA architecture;

FIG. 7A depicts one embodiment of the logic to select a translation mechanism;

FIG. 7B depicts one embodiment of the logic performed by a hypervisor to handle a fault resulting from address translation;

FIG. 8 depicts one embodiment of a radix translation mechanism;

FIG. 9 depicts one example of a radix on radix translation mechanism;

FIG. 10 depicts one example of a radix on hash page table translation mechanism;

FIG. 11 depicts one example of using a translation structure of one type to point to a translation structure of another type to perform address translation;

FIG. 12 depicts one embodiment of a radix on offset translation mechanism;

FIG. 13 depicts one example of a hash page table translation mechanism;

FIG. 14 depicts one example of a dynamic address translation (DAT) mechanism; and

FIG. 15 depicts one embodiment of a computer program product incorporating one or more aspects.

DETAILED DESCRIPTION

In one aspect, a system configuration is provided that has different types of translation structures available to it for use in translating memory addresses from one format (e.g., an effective address, and in particular, a virtual address associated therewith) to another format (e.g., a real address). Multiple translation structure formats (e.g., multiple page table formats, such as hash page tables and hierarchical page tables) are concurrently supported in a system configuration, and a control is provided to select, for a particular address to be translated, one or more types of translation structures to be used in the translation. In one embodiment, the different types of translation structures are structurally different, and include, for instance, hash structures, hierarchical structures and/or offset structures, which are described below.

Computing environments of different architectures may incorporate and use one or more aspects of the address translation capability provided herein. For instance, environments based on the PowerPC architecture, also referred to as Power ISA, offered by International Business Machines Corporation and described in the Power ISA™ Version 2.06 Revision B specification, Jul. 23, 2010, incorporated herein by reference in its entirety, may include one or more aspects, as well as computing environments of other architectures, such as the z/Architecture, offered by International Business Machines Corporation, and described in z/Architecture—Principles of Operation, Publication No. SA22-7932-08, 9th Edition, August 2010, which is hereby incorporated herein by reference in its entirety.

One example of a computing environment to incorporate and use one or more aspects of the translation capability is described with reference to FIG. 1A. In one example, a computing environment 100 includes a processor (central processing unit—CPU) 102 that includes at least one memory management unit (MMU)/translation lookaside buffer (TLB) portion 104 and a cache 106. Processor 102 is communicatively coupled to a memory portion 108 having a cache 110, and to an input/output (I/O) portion 112. I/O portion 112 is communicatively coupled to external I/O devices 114 that may include, for example, data input devices, sensors and/or output devices, such as displays.

Memory management unit 104 is used in managing memory portion 108 including facilitating access to the memory by providing address translation. To improve address translation, the memory management unit utilizes a translation lookaside buffer (TLB). The TLB is a cache of previously translated addresses. Thus, when a request is received for a memory access that includes an address to be translated, the TLB is checked first. If the address and its translation are in the TLB, then no translation is necessary. Otherwise, the received address is translated using one of any number of translation techniques.

A further embodiment of a computing environment to incorporate and use one or more aspects of the present invention is depicted in FIG. 1B. In this example, a computing environment 150 includes a server 152 that includes, for instance, one or more virtual machines 154, one or more central processors (e.g., central processing units) 156, at least one hypervisor 158, and an input/output subsystem 160. The virtual machines and hypervisor are included in memory 162.

In this embodiment, each virtual machine is capable of hosting a guest operating system 168 and may be executing one or more applications 170. An operating system or application running in a virtual machine appears to have access to a full complete system, but in reality, only a portion of it is available.

Central processors 156 (e.g., central processing units) are physical processor resources that are assignable to a virtual machine. For instance, virtual machine 154 includes one or more logical processors, each of which represents all or a share of a physical processor 156 that may be dynamically allocated to the virtual machine. Virtual machines 154 are managed by hypervisor 158, such as PowerVM, offered by International Business Machines Corporation, as examples.

Central processor 156, like CPU 102, includes at least one MMU/TLB portion and at least one cache.

Input/output subsystem 160 directs the flow of information between devices and memory (also referred to herein as main memory or main storage). It is coupled to the server in that it can be part of the server or separate therefrom. The I/O subsystem relieves the central processors of the task of communicating directly with the I/O devices coupled to the server and permits data processing to proceed concurrently with I/O processing.

Further details regarding the physical memory used by either system, such as memory 108 or memory 162, and access thereto are described with reference to FIG. 2A. As is known, physical memory is of a defined size and in order to have the physical memory appear larger than it is, virtual memory is utilized. One example of a high-level view of virtual memory 201 mapped to a physical memory 203 (such as memory 108, 162) is depicted in FIG. 2A. In this example, the mapping from virtual memory to real memory is via a hash page table (HPT) technique 205 to locate page table entries (PTEs), as used by, for example, Power ISA. In this example, programs only use sections A and B of the virtual memory. Each segment of the virtual memory is mapped to a segment ID (SID) entry 207 identified by an effective segment ID (ESID) (ESIDs for B and ESIDs for A included). An “effective address” 204 used by the program selects an SID entry, which includes the ESID value, as well as a virtual segment ID (VSID) 214 value. The VSID value represents the high-order bits of a virtual address to be used by hashing algorithm 205 to search the hash page table. A hashed value based on the VSID is used to locate a page table entry (PTE). The page table entry includes an address 213 of a page of physical memory 203.

FIG. 2B illustrates an example of a technique for generating a virtual address 202 for hashing. In this regard, an effective address 204 is received in, for instance, a memory management unit of a processor. Effective address 204 includes an effective segment identifier (ESID) field 206, a page field 208 and byte offset field 210. The ESID field is used to locate an entry in a segment lookaside buffer (SLB) 212, which is a cache of recently accessed segment ID entries. In particular, the SLB is searched for an entry with a value of ESID 206 of the effective address 204. The entry with the ESID 206 includes an associated virtual segment identifier (VSID) 214, as well as other information, as described below. The associated VSID is used to generate virtual address 202, which includes VSID 214; and page 208 and byte 210 from the effective address 204. Virtual address 202 is used to obtain a real address used to access physical memory in the memory system. In this disclosure, the terms physical memory, real memory, system memory and absolute memory are used interchangeably to refer to the main storage accessible to a processor.

FIG. 2C illustrates an example of a hash page table (HPT) translation structure used by Power ISA. ESID portion 206 of an effective address (EA) 204 is used to locate an entry in SLB 212. The entry includes a VSID field 214. The value of VSID field 214 and a portion of EA 204 (page.byte) are hashed 230 to produce a hash value that is used to locate a page table entry (PTE) group 252 in a hash page table (HPT) 250. Page table entries 253 of PTE group 252 are searched to locate a corresponding PTE having a field matching a value of a most-significant-portion of the VSID. When a corresponding PTE is found, the address (e.g., real address) of the physical memory page in the PTE is used to access physical memory. In order to improve performance, once a PTE entry is found, the page portion 208 of EA 204 and the address of the physical memory page found in the PTE are stored in TLB 254, such that further accesses to the same EA page will “hit” in TLB 254 and avoid the PTE search. The page table is located by a page table origin address provided by the processor.

Further details regarding a segment lookaside buffer and a page table are described with reference to FIGS. 3 and 4A-4B. Referring initially to FIG. 3, a segment lookaside buffer (SLB) 212 specifies the mapping between effective segment IDs (ESIDs) and virtual segment IDs (VSIDs). The number of SLB entries (SLBE) in an SLB is implementation dependent, and in one example, includes at least 32 entries. In one example, segment lookaside buffer 212 includes a plurality of SLB entries 300, and each SLB entry 300 maps one ESID 302 to one VSID 308. In one example, SLBE 300 includes the following fields:

-   -   Effective segment ID (ESID) 302 (bits 0-35);     -   Entry valid indicator (V) 304 (bit 36) which indicates whether         the entry is valid (V=1) or invalid (V=0);     -   Segment sized selector (B) 306 (bits 37-38), which has the         following meaning, in one example: 0b00—256 Megabytes (MB)         (s=28), 0b01—1 Terabyte (TB) (s=40), 0b10—256 TB (s=48), and         0b11—reserved;     -   Virtual segment ID (VSID) 308 (bits 39-88);     -   Supervisor (privileged) state storage key indicator (K_(s)) 310         (bit 89);     -   Problem state storage key indicator (K_(r)) 312 (bit 90);     -   No-execute segment if N=1 indicator (N) 314 (bit 91);     -   Virtual page size selector bit 0 (L) 316 (bit 92);     -   Class indicator (C) 318 (bit 93);     -   Virtual page size selector bits 1:2 (LP) 322 (bits 95-96); and     -   Radix segment indicator (RS) 326 (bit 99), which, in one         example, 0 indicates disabled and 1 indicates enabled. When         RS=1, the virtual address used for the hash page table search         has the lowest S (encoded in SLBE_(B)) number of bits set to         zero.

In one embodiment, instructions cannot be executed from a no-execute (N=1) segment. Segments may contain a mixture of page sizes. The L and LP bits specify the base virtual page size that the segment may contain. The SLB_(L∥Lp) encodings are those shown below, in one example:

encoding base page size 0b000  4 KB 0b101 64 KB additional values 2^(b) bytes, where b > 12 and b may differ among encoding values, where the “additional values” are implementation-dependent, as are the corresponding base virtual page sizes. The values that are not supported by a given implementation are reserved in that implementation.

The base virtual page size also referred to as the base page size is the smallest virtual page size for the segment. The base virtual page size is 2^(b) bytes. The actual virtual page size (also referred to as the actual page size or virtual page size) is specified by PTE_(L∥LP).

The Class field is used in conjunction with the SLB Invalidate Entry (SLBIE) and SLB Invalidate All (SLBIA) instructions. Class refers to a grouping of SLB entries and implementation-specific lookaside information so that only entries in a certain group need be invalidated and others might be preserved. The class value assigned to an implementation-specific lookaside entry derived from an SLB entry is to match the class value of that SLB entry. The class value assigned to an implementation-specific lookaside entry that is not derived from an SLB entry (such as real mode address translations) is 0.

Software is to ensure that the SLB contains at most one entry that translates a given instruction effective address. An attempt to create an SLB entry that violates this requirement may cause a machine check.

As described herein, at least one field of the SLB is used to access a page table, and in particular, a specific page table entry. Further information regarding a page table and page table entries is described with reference to FIGS. 4A-4B. In this example, the page table and its corresponding entries are for the Power ISA architecture; however, other page tables and entries may be used for other architectures.

Referring initially to FIG. 4A, a page table 400 includes one or more page table entries 402. As one example, page table 400 is a hash page table (HPT), which is a variable-sized data structure that specifies the mapping between virtual page numbers (VPN) and real page numbers (RPN), where the real page number of a real page is, for instance, bits 0:47 of the address of the first byte in the real page. The hash page table size can be any size 2^(n) byteswhere 18<n<46. The hash page table is to be located in storage having the storage control attributes that are used for implicit accesses to it. In one embodiment, the starting address is to be a multiple of its size unless the implementation supports a server.relaxed page table alignment category, in which case its starting address is a multiple of 2¹⁸ bytes, as an example.

In one example, the hash page table contains page table entry groups (PTEGs). A page table entry group contains, for instance, eight page table entries of 16 bytes each; each page table entry group is thus 128 bytes long. PTEGs are entry points for searches of the page table.

Further details of a page table entry are described with reference to FIG. 4B. Each page table entry 402 maps one virtual number to one real page number. As an example for the Power ISA architecture, a page table entry includes the following:

Dword Bit(s) Name Description 0 0:1 B (404) Segment Size 0b00 - 256 MB; 0b01 - 1 TB; 0b10 - 256 TB; 0b11 - reserved  2:56 AVA (406) Abbreviated Virtual Address 57:60 SW (408) Available for software use 61 L (410) Virtual page size 0b0 - 4 KB 0b1 - greater than 4 KB (large page) 62 H (412) Hash function identifier 63 V (414) Entry valid (V = 1) or invalid (V = 0) 1  0 PP (416) Page Protection bit 0  1 / Reserved 2:3 Key (420) KEY bits 0:1  4:43 ARPN (422) Abbreviated Real Page Number 44:51 LP (424) Large page size selector  4:51 RTABORG Virtualized real address of Radix Table (426) (when SLBE_(RS) = 1 or VRMASD_(RS) = 1) 52:54 Key (428) KEY bits 2:4 55 R (430) Reference bit 56 C (432) Change bit 57:60 WIMG (434) Storage control bits 61 N (436) No-execute page if N = 1 62:63 PP (438) Page Protection bits 1:2

Further details regarding one implementation of page tables and page table entries are described in Power ISA™ Version 2.06 Revision B specification, Jul. 23, 2010, offered by International Business Machines Corporation and incorporated herein by reference in its entirety.

The use of a hash page table to translate addresses is only one example of a translation technique. Other address translation schemes, including those that use a hierarchy of translation tables, are described below, as well as in the following publications: z/Architecture—Principles of Operation, Publication No. SA22-7932-08, 9th Edition, August 2010, and Intel Itanium Architecture Software Developer's Manual Volume 2: System Architecture, Document Number: 245318-005, each hereby incorporated herein by reference in its entirety. In one example, for the z/Architecture, the hierarchy of tables is referred to as dynamic address translation (DAT) tables; and for Power ISA, the tables are referred to as radix tables.

One example of a hierarchical translation table translation mechanism is described with reference to FIG. 5A. In this example, translation tables 504 are provided for translating addresses of virtual memory 502, though only regions A and B are to be used, in this example, to real addresses. The origin of the highest order translation table of the hierarchical translation tables 504, is provided, for example, by a control register (CR3) 506. An effective address 508 is used to index into each table of the hierarchical translation tables 504 to determine an origin address of the next table until, for example, a page table entry (PTE) having an address 509 of a page of physical memory 510 is located. In one example in which the translation mechanism is DAT, the effective address is a virtual address having a plurality of indices used to index into the translation tables.

FIG. 5B shows one example in which the highest level translation table of the hierarchy is “indexed” by the high portion 508 a of an effective address 508 to locate a Table 1 entry 512 a that is used to locate the next translation table (Table 2). That is, entry 512 a includes an origin address of Table 2. Similarly, a next portion 508 b of the effective address 508 is used to index into Table 2 to find a Table 2 entry 512 b having the origin address of Table 3. A next portion of the effective address 508 c is used to index into Table 3 to find a Table 3 entry 512 c having an origin address of a Page Table 514 a. A next portion 508 d of the effective address 508 is used to index into Page Table 514 a to locate a page table entry 512 d having the address of a physical memory page 516. The origin of the hierarchy of translation tables, in one embodiment, may include a table selector field for determining which of the hierarchy of translation tables, the origin applies. Thus, the translation may require only a subset of the hierarchy (wherein an effective address is limited to include a predetermined number of most significant bits having a zero value). A translation using fewer tables will be faster than one using more tables.

The page table entry located by traversing the hierarchical page tables includes various information including at least a portion of a real address used to access the physical memory. The format and information included in the page table entry depends on the architecture of the system configuration and/or the specific type of translation.

In one example in which the address translation is the DAT translation of the z/Architecture, a page table entry 600 includes the following, as depicted in FIG. 6A:

-   -   Page-Frame Real Address (PFRA) (602): Bits 0-51 provide the         leftmost bits of a real storage address. When these bits are         concatenated with the 12-bit byte index field of the virtual         address on the right, a 64-bit real address is provided;     -   Page-Invalid bit 604 (I): Bit 53 controls whether the page         associated with the page table entry is available. When the bit         is zero, address translation proceeds by using the page table         entry. When the bit is one, the page table entry is not to be         used for translation;     -   DAT-Protection Bit (P) 606: Bit 54 controls whether store         accesses can be made in the page. This protection mechanism is         in addition to the key-controlled-protection and         low-address-protection mechanisms. The bit has no effect on         fetch accesses; and     -   Change-Recording Override (CO) 608: When enhanced DAT does not         apply, bit 55 of the page-table entry is to contain zero;         otherwise, a translation-specification exception is recognized         as part of the execution of an instruction using that entry for         address translation. When enhanced DAT applies and a segment         table entry (STE) format control is zero, bit 55 of the         page-table entry is the change-recording override for the page.

As a further example in which the address translation is the radix translation of Power ISA, a page table entry includes the following fields, as depicted in FIG. 6B. The format of this page table entry includes at least some fields similar to the fields of the page table entry obtained using the hash technique for Power ISA. In one example, page table entry 650 includes:

Bits Name Description  0 N (652) No-execute page if N = 1  1 PP (654) Page Protections 0 2-6 Key (656) KEY bits 0:4  7-51 AA (658) Abbreviated Address (concatenated with twelve zeros) 52-54 SO (660) Available for software 55 G (662) Guarded 56 L (664) Leaf 0 - is Page Directory Entry (PDE) (0-1, 52-55, 57-62 ignored) 1 - is Page Table Entry (PTE) 57 C (666) Changed 58 R (668) Reference 59 I (670) Cache Inhibited 60 W (672) Writethrough 61-62 PP (674) Page Protections 1:2 63 V (676) Valid Entry Indicator

In accordance with one aspect, a system configuration is provided with different types of address translation structures for use in translating addresses. As examples, one type uses a hierarchical data structure (e.g., a radix structure), and another type uses a hash data structure. Other and/or different types of structures may also be used, including, for instance, a combination of a hierarchical and a hash structure, or an offset structure, as examples. Further, in one example, the type of translation structure to be used for a particular translation is selectable.

One embodiment of the logic to select from a plurality of translation mechanisms to translate an address is described with reference to FIG. 7A. In this example, the environment is a virtualized environment having one or more guests (e.g., guest operating systems executing within partitions) supported by a host (e.g., a host machine, including a host operating system and/or a hypervisor), and the address being translated is a guest virtual address (obtained based on an effective address) to a host physical address (a.k.a., host real address). In one embodiment, hardware of the environment (e.g., the MMU) is used to perform the logic of FIG. 7A, unless otherwise noted. In a further embodiment, hardware and/or firmware is used to perform the logic. As used herein, firmware includes, e.g., the microcode, millicode and/or macrocode of the processor. It includes, for instance, the hardware-level instructions and/or data structures used in implementation of higher level machine code. In one embodiment, it includes, for instance, proprietary code that is typically delivered as microcode that includes trusted software or microcode specific to the underlying hardware and controls operating system access to the system hardware.

Referring to FIG. 7A, initially, the hardware within a partition (e.g., MMU of a processor within the virtualized environment) receives a memory access request which includes a memory address translation request for an effective address, STEP 700. The memory address request may be a memory operation to load/store, a memory operand in an instruction, an instruction address to be accessed during an instruction fetch, a load real address, or a prefetch instruction, as examples.

Based on the effective address in the translation request, a guest virtual address is obtained and translated within the partition to a guest physical address using a selected translation format, such as, for instance, a radix translation, STEP 702. A determination is made as to whether a translation event has occurred based on the translation from the guest virtual address to the guest physical address, INQUIRY 704. If a translation event has occurred, then that event (e.g., radix table miss), along with the guest virtual address, is presented from the hardware to the operating system using an instruction storage interrupt (ISI) or data storage interrupt (DSI) depending on whether the translation that resulted in a fault corresponded to an instruction or data access, STEP 706. However, if there was no translation event, then the guest virtual address has been translated to the guest physical address.

Next, a determination is made as to the type of translation to be selected to translate the guest physical address to the host physical address, INQUIRY 708. In the example herein, it is either a hierarchical translation mechanism (e.g., radix) or a hash page table translation mechanism that is selected; however, in other embodiments, other types of translation mechanisms may be selected, such as an offset mechanism or other types. In one embodiment, the selection of the translation mechanism is dependent on the type of hypervisor that is configuring the system for translation, and the preference of that hypervisor; and/or the selection may be based on the condition of the memory. For instance, if host memory has little fragmentation or large pages, a radix or other hierarchical translation may be selected; for heavily fragmented host memory, hash page table translation may be selected; and for static partitions, an offset translation mechanism may be selected. Other selection criteria are also possible.

Further, in one embodiment, selection may be performed at various levels of translation including, for instance, from guest virtual to guest physical, and/or from guest physical to host physical, and each selection is independent of the other. That is, the selection of a particular structure at one level (e.g., guest level) has no bearing on the selection at another level (e.g., host level).

The selection, in one example, is configured by the hypervisor for the system by setting one or more indicators in one or more control registers, other registers, or memory, subsequent to making the selection and prior to receiving a translation request. In another example, the selection is made dynamically by, for instance, the hypervisor or operating system, at the time of the translation, and that selection is provided to the hardware or firmware.

Continuing at INQUIRY 708, if a radix (or other hierarchical) translation is selected for the host translation, then the guest physical address is translated to the host physical address using a radix (or other hierarchical) translation, STEP 710. However, if hash page table translation has been selected, then the guest physical address is translated to the host physical address using a hash page table translation, STEP 712. Other translation mechanisms may also be selected, although, not shown in this particular example.

If a translation event occurs during translation of the guest physical address to the host physical address, INQUIRY 714, then that event is indicated to the hypervisor via a host instruction storage interrupt (HISI)/host data storage interrupt (HDSI), in which the guest's physical address is specified, STEP 716. If a translation event has not been indicated, then the guest physical address has been translated to the host physical address, and the host physical address is usable for the memory access.

Should the hypervisor be interrupted via an HISI or HDSI, the hypervisor performs certain processing, an example of which is depicted and described with reference to FIG. 7B. Initially, the hypervisor receives the HISI/HDSI, STEP 760. Thereafter, in one embodiment, a determination is made as to whether radix guest translation is enabled, INQUIRY 762. In one example, this is determined by an indicator in a control register or other register. If radix guest translation is not enabled, then HPT event handling for HPT memory translation is performed as usual, STEP 764. For instance, the hypervisor reloads the HPT. Further, execution of the instruction that caused the HISI/HDSI is restarted, STEP 766.

Returning to INQUIRY 762, if radix guest translation is enabled, in one embodiment, the partition fault address (e.g., the guest physical address) to be translated is obtained by the operating system from the hardware, STEP 768. Further, a translation entry for that address is obtained from a memory map to load the host translation table, STEP 770. The translation entry that is obtained is installed in the host translation table (e.g., HPT or radix, in a further embodiment), STEP 772, and execution of the instruction having caused the HISI/HDSI is restarted, STEP 774.

For example, in one embodiment, host translation is performed using an HPT structure. In accordance with this embodiment, further to STEP 768, a translation entry for that address is obtained from a memory map to load the HPT, STEP 770. In accordance with another embodiment and in another execution, a host physical page has been paged out and is paged in prior to installing a translation entry. The translation entry that is obtained is installed in the HPT, STEP 772, and execution of the instruction having caused the HISI/HDSI is restarted, STEP 774. In another embodiment, host translation is performed by a radix structure. In accordance with this embodiment, further to STEP 768, a translation fault is handled for a radix table, e.g., a translation entry for that address is obtained from a memory map to load the radix table, STEP 770. In accordance with another embodiment and in another execution, a host physical page has been paged out and is paged in prior to installing a translation entry. The translation entry that is obtained is installed in the radix table, STEP 772, and execution of the instruction having caused the HISI/HDSI is restarted, STEP 774.

Further details regarding different types of translation structures, including a hierarchical translation structure, such as a radix translation structure, and variations thereof, such as a radix on radix translation structure (i.e., using a radix table for guest translation in conjunction with a radix table for host translation), and a radix on hash page table (HPT) translation structure (i.e., using a radix table for guest translation in conjunction with an HPT table for host translation) are described below with reference to FIGS. 8-10.

Referring initially to FIG. 8, one embodiment of the logic to translate a virtual address to a physical address using radix translation is described. As shown, a radix table origin stored in, for instance, a register 800 indicates the beginning of a radix translation structure 802. Radix translation structure 802, also referred to as a radix page table (RTAB), is for instance, a hierarchical, variable sized data structure that specifies the mapping between virtual page numbers and real page numbers, virtual page numbers and virtualized real page numbers, or virtualized real page numbers and real page numbers, where the real page number of a real page is, for instance, bits 0-44 of the address of the first byte of the real page. The RTAB is located in storage having the storage control attributes that are used for implicit access to it. The starting address is aligned in one example to a 4K boundary. The RTAB includes a series of 512-entry tables, in one embodiment.

In one example, radix translation structure 802 includes, for instance, a plurality of radix structures, including a level 4 page directory (PD) 802 a, a level 3 page directory 802 b, a level 2 page directory 802 c, and a level 1 page table (PT) 802 d. Each page directory and page table includes a plurality of entries, referred to herein as page directory entries (PDEs) or page table entries (PTEs), respectively. (The L field of an entry indicates whether there are additional entries to be used in the translation.) The structures are indexed into, in this example, using a page number 810 generated from a segment offset 812 of the effective address.

To index into radix structure 802, as one example, the first X (e.g., 9) bits of page number 810 are used as an offset into PD 802 a pointed to by radix table origin 800. The contents of a selected PDE of PD 802 a provide an address of PD 802 b, and the next X bits of page number 810 are used to index into PD 802 b to obtain an address of PD 802 c. Further, the next X bits of page number 810 are used to access a selected PDE of PD 802 c to obtain the address of the page table 802 d. The last X bits of page number 810 are used to access a selected PTE of PT 802 d. The output of the PTE of PT 802 d combined with byte portion 814 of segment offset 812 creates a physical address 816, also known as a real address.

The above describes one embodiment of translating a virtual address to a physical address using radix translation. However, in the situation in which the virtual address is a guest virtual address, additional processing may be used to translate each guest address to a corresponding host address. One embodiment of this logic is described with reference to FIG. 9, which shows an example of a radix on radix translation mechanism. That is, radix is used for the guest translations, as well as the host translations.

Referring to FIG. 9, a radix on radix translation mechanism includes a radix guest structure 902 and a radix host structure 904. Radix translation structure 902 is similar to radix structure 802 of FIG. 8 and includes a plurality of radix structures, including a level 4 PD 902 a, a level 3 PD 902 b, a level 2 PD 902 c, and a level 1 PT 902 d, each including a plurality of entries. Similarly, radix host structure 904, which is repeatedly shown for clarity, also includes a plurality of radix structures including a level 4 PD, a level 3 PD, a level 2 PD and a level 1 PT, and each includes a plurality of PDEs or PTEs. A guest page table pointer 900 (also referred to as a virtual real address of a guest level 4 table) is translated by radix host structure 904 to provide a real address of the guest level 4 table of radix guest translation structure 902. For instance, the bits of the virtual real address of the level 4 table are used to walk host radix structure 904, as described above with reference to FIG. 8, to obtain a real address of level 4 PD 902 a. As an example, the first X (e.g., 9) bits of virtual real address 900 are used to index into a level 4 PD of structure 904 to obtain from its entry an address of a level 3 PD of structure 904. The next X bits of virtual real address 900 are used to index into the level 3 PD of structure 904 to obtain an address of the level 2 PD of structure 904. The next X bits of address 900 are used to index into the level 2 PD of structure 904 to obtain an address of the level 1 PT of structure 904, and the next X bits of address 900 are used to index into the level 1 PT of structure 904 to obtain a real address of level 4 PD 902 a.

Then, in guest structure 902, the first X (e.g., 9) bits of the effective address (not shown) to be translated are used to index into the level 4 PD 902 a to obtain a virtual real address of level 3 PD 902 b. This virtual address is translated into a real address of level 3 PD 902 b using radix host structure 904, which is indexed into using the bits of the virtual real address of the level 3 PD, as described above. The second set of X bits of the effective address is then used to index into PD 902 b to obtain a virtual real address of level 2 PD 902 c. That address is then translated using host structure 904 to obtain a real address of level 2 PD 902 c. The third set of X bits of the effective address is used to index into PD 902 c to obtain a virtual real address of PT 902 d. The virtual real address is then translated using radix host structure 904 to obtain a real address of level 1 PT 902 d. The next X bits of the effective address are used to index into PT 902 d to obtain a virtual real address. The virtual real address is translated using radix host structure 904, and the output of that translation combined with a byte offset of the effective address is a host physical address 906. In one example, using this type of translation, it takes 24 reads to translate an address, in the worst case.

In addition to the above, a radix on hash page table (HPT) translation mechanism is provided, in which the guest translations are via a radix structure and the host translations are via a hash page table structure. An example of a radix on hash page table translation is described with reference to FIG. 10. Referring to FIG. 10, a guest page table pointer 1000 (also referred to as a virtual real address of level 4 table (1004 a)) is input to a host hash page table 1002 to translate address 1000 to a real address of level 4 PD 1004 a of a guest radix translation structure 1004. Similar to the radix structures described above, radix translation structure 1004 includes a plurality of radix translation structures, including, for instance, a level 4 PD 1004 a, a level 3 PD 1004 b, a level 2 PD 1004 c, and a level 1 PT 1004 d, and in this case, the real address of level 4 structure 1004 a, referred to as a level 4 page directory (PD), is obtained from HPT 1002.

The first X (e.g., 9) bits of the effective address to be translated are used to index into PD 1004 a to obtain the pertinent contents. As in each of these translations, the contents of the selected level 4 page directory entry of PD 1004 a are checked to see if there are additional levels to be searched (e.g., is L=0), and if so, the virtual real address of PD 1004 b is used to hash into HPT 1002. Based thereon, the real address of a level 3 PD structure 1004 b is obtained. The next X bits of the effective address are used to index into PD 1004 b and this access provides a virtual real address of a level 2 structure 1004 c. This virtual address is used in hash structure 1002 to obtain a real address of structure 1004 c. The next X bits of the effective address are used to index into PD 1004 c to obtain a virtual real address of level 1 PT 1004 d, which is used to access the HPT. The output of the HPT access is the real address of a level 1 table 1004 d, which is used to obtain another virtual real address. Since implicitly L=1 as all levels in the page table have been exhausted, this is the last table of the radix structure, and therefore, this entry is the page table entry. The next X bits of the effective address are used to index into the page table to provide the guest physical address. The guest physical address is used to access the hash table. The output of the hash table combined with a byte offset of the effective address provides the host physical address 1006 corresponding to the effective address being translated.

In one embodiment, the guest page table pointer (e.g., guest page table pointer 1000; a.k.a., the virtual real address of the first table in the hierarchy of tables) is obtained using the hash table. This is described with reference to FIG. 11. As shown, in this example, if SLBE_(RS)=1 (1100), a PTE (1102) found during a hash PTE search is an indirect PTE used to point to a hierarchical page table 1104 that can be manipulated by non-hypervisor code. In this example, the hierarchical page table is a radix page table (RTAB) to be used by, for instance, the Power ISA architecture, along with the hash table. The ARPN and LP fields of the hash page table entry (located during a hash translation) are replaced by the RTABORG, which is the virtualized real address of the radix page table. The radix page table is then used, in one example, to obtain a virtual real address (a.k.a., guest physical address) of physical memory to be accessed. The virtual real address is then converted, in one embodiment, to a host physical address via, for instance, a hash mechanism (see, e.g., FIG. 10) or a radix mechanism (see, e.g., FIG. 9).

More specifically, if the indicator specifies that multiple types of translation formats are to be used to translate the effective address of the request to a real address (i.e., SLBE_(RS=1)), then processing continues with obtaining the VSID from the SLBE. The VSID is used to locate an entry in one type of table (e.g., the hash table) in order to obtain the root of a another type of table (e.g., a hierarchical table, such as a radix table). In particular, in one example, the VSID is used to create a canonical address used to index into the HPT to obtain the RTABORG. A canonical address is an address created for a plurality of pages in a segment. That is, a particular segment includes a plurality of pages that share the same radix table. Therefore, the address used to index into HPT is to be the same for all those pages. In order to create the canonical address, the low order address bits for all the addresses that share the same radix table are zeroed out (and in one embodiment an appropriate constant is added). For instance, the virtual address obtained based on the effective address includes the VSID, and page and byte offsets. The VSID is used (optionally, along with the constant) to create the canonical address. The canonical address is used to index into the HPT to obtain the origin of the radix table (i.e., the virtual real address of the first table in the hierarchy of tables to be used in translation).

In addition to, or in lieu of, the translation mechanisms described above, other translation mechanisms may be used. One example of another type of translation mechanism is a radix on offset mechanism, in which a radix guest translation mechanism is used in conjunction with a host translation based on a real mode base and a real mode limit, an example of which is described with reference to FIG. 12.

In this example, translation is performed using a real mode offset register (RMOR) and a real mode limit selector (RMLS) 1202 and a radix structure 1204. As described previously, radix structure 1204 includes, in this example, a level 4 PD 1204 a, a level 3 PD 1204 b, a level 2 PD 1204 c and a level 1 PT 1204 d, each including a plurality of PDEs or PTEs. A guest page table pointer 1200 (a.k.a., a virtual real address of PD 1204 a) is translated to a real address of PD 1204 a using a real mode offset register (RMOR) value and a real mode limit selector (RMLS). The RMOR is added to address 1200 and the result of the addition is compared to RMLS. If it is less than the limit, in this example, then the result is used to access PD 1204 a of radix table 1204. The radix table is walked, as described herein (e.g., using first X (e.g., 9) bits of the effective address), to obtain from the selected PDE of PD 1204 a a virtual real address of PD 1204 b. The base and limit are used again, but this time with the virtual real address of PD 1204 b to obtain the real address of PD 1204 b. Translation continues and when the selected PTE of PT 1204 d is located, a guest physical address is obtained which is translated using host structure 1202 to obtain an address that when concatenated with a byte offset of the effective address provides a host physical address to be used in translation.

Described in detail above are aspects in which multiple types of translation structures are included in a configuration, and it is selectable as to which translation mechanism(s) may be used to translate an effective address to a host real address. However, if the system configuration does not support such a feature or if it supports that feature, as well as legacy translation techniques, then legacy translation is provided.

One embodiment of the logic of a legacy translation technique in which a hash page table is used is described with reference to FIG. 13. Initially, an address request is received that includes an effective address, STEP 1300. The effective address is used to generate a virtual address, STEP 1302. For instance, the ESID is used to locate an SLBE, which includes a VSID. The VSID combined with the page.byte of the effective address provides the virtual address to be translated. Thus, the virtual address is created by address substitution (referred to herein as segmentation) and not using paging support. Thereafter, a determination is made as to whether there is an SLB address generation event, INQUIRY 1304. For instance, was there a miss in the SLB when looking for the ESID? If not, then the virtual address is translated to a real address using conventional HPT translation, STEP 1306. A determination is made as to whether there is a translation event, INQUIRY 1308. If there is no HPT translation event, then processing is complete, and the real address can be used to access memory.

Returning to INQUIRY 1308, if there is an HPT translation event, then the translation event is specified to either the operating system or hypervisor using, for instance, ISI/DSI or HISI/HDSI, STEP 1310. HPT event processing is performed, including optionally performing paging, STEP 1312. The operating system or hypervisor restarts the instruction, STEP 1314, and the flow returns to STEP 1300.

Returning to INQUIRY 1304, if there is an SLB generation event, then an SLB event is indicated to the operating system, STEP 1320. Further, SLB event processing is performed including, for instance, reloading the SLB (excluding paging), STEP 1322. The operating system restarts the instruction, STEP 1324, and processing continues with STEP 1300.

A further legacy technique for translating memory addresses is described with reference to FIG. 14. This technique uses a hierarchical translation mechanism. Initially, an address request is received, STEP 1400. The address is translated using, for instance, DAT translation, STEP 1402. One example of an architecture that uses DAT translation is the z/Architecture, which is described in an IBM Publication entitled “z/Architecture—Principles of Operation,” Publication No. SA22-7932-08, 9^(th) Edition, August 2010, which is hereby incorporated herein by reference in its entirety. Thereafter, a determination is made as to whether there was a DAT translation event, such as a miss, INQUIRY 1404. If not, then the address has been translated to the physical address, STEP 1406, and processing is complete.

However, if there is a DAT translation event, INQUIRY 1404, then the translation event is either indicated to the operating system or hypervisor, STEP 1410. DAT event processing is performed in the operating system or hypervisor; optionally, performing paging, STEP 1412. Further, the operating system or the hypervisor restarts the instruction, STEP 1414, and processing continues to STEP 1400.

Described in detail above is a capability for selecting from multiple types of translation structures to translate an effective address to a real address. Although examples of translation mechanisms are described, additional and/or different mechanisms may be used. In one example, a first address (e.g., a guest virtual address) is translated to a second address (e.g., a guest physical address) using a scheme selected from, for instance, radix translation, other hierarchical translation, segmentation (e.g., using SLB), hash page table or a combination of the above, as examples. The second address is translated to a third address (e.g., a host physical address) using a translation scheme selected from one or more of page level schemes (translation schemes other than offset mechanisms); radix mechanisms; other hierarchical mechanisms; hash mechanisms; or offset mechanisms, as examples.

In one embodiment, the third address (e.g., host physical address) corresponds to an address executing in a hypervisor partition executing under control of another level of virtualization. That is, the third address is yet another virtual address to be translated to a physical address. The translation is performed as above, and the translation mechanisms are again independently selectable.

As will be appreciated by one skilled in the art, aspects of the present invention may be embodied as a system, method or computer program product. Accordingly, aspects of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, micro-code, etc.) or an embodiment combining software and hardware aspects that may all generally be referred to herein as a “circuit,” “module” or “system”. Furthermore, aspects of the present invention may take the form of a computer program product embodied in one or more computer readable medium(s) having computer readable program code embodied thereon.

Any combination of one or more computer readable medium(s) may be utilized. The computer readable medium may be a computer readable signal medium or a computer readable storage medium. A computer readable signal medium may include a propagated data signal with computer readable program code embodied therein, for example, in baseband or as part of a carrier wave. Such a propagated signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical or any suitable combination thereof. A computer readable signal medium may be any computer readable medium that is not a computer readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus or device.

A computer readable storage medium may be, for example, but not limited to, an electronic, magnetic, optical, electromagnetic, infrared or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing. In the context of this document, a computer readable storage medium may be any tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device.

Referring now to FIG. 15, in one example, a computer program product 1500 includes, for instance, one or more non-transitory computer readable storage media 1502 to store computer readable program code means or logic 1504 thereon to provide and facilitate one or more aspects of the present invention.

Program code embodied on a computer readable medium may be transmitted using an appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

Computer program code for carrying out operations for one or more aspects may be written in any combination of one or more programming languages, including an object oriented programming language, such as Java, Smalltalk, C++ or the like, and conventional procedural programming languages, such as the “C” programming language, assembler or similar programming languages. The program code may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet Service Provider).

One or more aspects are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer readable medium that can direct a computer, other programmable data processing apparatus, or other devices to function in a particular manner, such that the instructions stored in the computer readable medium produce an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide processes for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

In addition to the above, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider who offers management of customer environments. For instance, the service provider can create, maintain, support, etc. computer code and/or a computer infrastructure that performs one or more aspects of the present invention for one or more customers. In return, the service provider may receive payment from the customer under a subscription and/or fee agreement, as examples. Additionally or alternatively, the service provider may receive payment from the sale of advertising content to one or more third parties.

In one aspect, an application may be deployed for performing one or more aspects of the present invention. As one example, the deploying of an application comprises providing computer infrastructure operable to perform one or more aspects of the present invention.

As a further aspect, a computing infrastructure may be deployed comprising integrating computer readable code into a computing system, in which the code in combination with the computing system is capable of performing one or more aspects of the present invention.

As yet a further aspect, a process for integrating computing infrastructure comprising integrating computer readable code into a computer system may be provided. The computer system comprises a computer readable medium, in which the computer medium comprises one or more aspects of the present invention. The code in combination with the computer system is capable of performing one or more aspects of the present invention.

Although various embodiments are described above, these are only examples. For example, computing environments of other architectures can incorporate and use one or more aspects of the present invention. Additionally, other types of translation structures may be used and other types of environments may benefit from one or more aspects. Additionally, the structures may have different fields and/or the fields can be of different sizes. Further, the number of bits used to index into a structure can be the same or different for each level, and/or for each structure. Many variations are possible.

Further, other types of computing environments can benefit from one or more aspects. As an example, an environment may include an emulator (e.g., software or other emulation mechanisms), in which a particular architecture (including, for instance, instruction execution, architected functions, such as address translation, and architected registers) or a subset thereof is emulated (e.g., on a native computer system having a processor and memory). In such an environment, one or more emulation functions of the emulator can implement one or more aspects of the present invention, even though a computer executing the emulator may have a different architecture than the capabilities being emulated. As one example, in emulation mode, the specific instruction or operation being emulated is decoded, and an appropriate emulation function is built to implement the individual instruction or operation.

In an emulation environment, a host computer includes, for instance, a memory to store instructions and data; an instruction fetch unit to fetch instructions from memory and to optionally, provide local buffering for the fetched instruction; an instruction decode unit to receive the fetched instructions and to determine the type of instructions that have been fetched; and an instruction execution unit to execute the instructions. Execution may include loading data into a register from memory; storing data back to memory from a register; or performing some type of arithmetic or logical operation, as determined by the decode unit. In one example, each unit is implemented in software. For instance, the operations being performed by the units are implemented as one or more subroutines within emulator software.

Further, a data processing system suitable for storing and/or executing program code is usable that includes at least one processor coupled directly or indirectly to memory elements through a system bus. The memory elements include, for instance, local memory employed during actual execution of the program code, bulk storage, and cache memory which provide temporary storage of at least some program code in order to reduce the number of times code must be retrieved from bulk storage during execution.

Input/Output or I/O devices (including, but not limited to, keyboards, displays, pointing devices, DASD, tape, CDs, DVDs, thumb drives and other memory media, etc.) can be coupled to the system either directly or through intervening I/O controllers. Network adapters may also be coupled to the system to enable the data processing system to become coupled to other data processing systems or remote printers or storage devices through intervening private or public networks. Modems, cable modems, and Ethernet cards are just a few of the available types of network adapters.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms “a”, “an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms “comprises” and/or “comprising”, when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and/or groups thereof.

The corresponding structures, materials, acts, and equivalents of all means or step plus function elements in the claims below, if any, are intended to include any structure, material, or act for performing the function in combination with other claimed elements as specifically claimed. The description of the present invention has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the invention. The embodiment was chosen and described in order to best explain various aspects and the practical application, and to enable others of ordinary skill in the art to understand the various embodiments with various modifications as are suited to the particular use contemplated. 

What is claimed is:
 1. A method of facilitating translation of memory addresses, said method comprising: obtaining, by a processor, a memory address to be translated, the processor having a first type of address translation structure and a second type of address translation structure available for translating the memory address, wherein the first type is structurally different from the second type; and selecting, by the processor, one type of address translation structure of the first type of address translation structure and the second type of address translation structure to be used in translating the memory address.
 2. The method of claim 1, further comprising: obtaining, by the processor, a first address to be translated to a second address; and using a third type of address translation structure to translate the first address to the second address, the second address being the memory address to be translated by the selected one type of address translation structure.
 3. The method of claim 2, wherein the selected one type of address translation structure is different from the third type of address translation structure.
 4. The method of claim 3, wherein the third type of address translation structure uses a hierarchical translation structure and the selected one type of address translation structure uses a hash translation structure.
 5. The method of claim 2, further comprising selecting the third type of address translation structure from a plurality of types of address translation structures.
 6. The method of claim 5, wherein the plurality of types of address translation structures include at least one of a hierarchical address translation structure, a hash translation structure, an offset translation structure, a combination type translation structure, and a segmentation type translation structure.
 7. The method of claim 5, wherein the selecting of the third type of address translation structure is independent of the selecting of the one type of address translation structure.
 8. The method of claim 2, wherein the first address comprises a guest virtual address, the second address comprises a guest physical address, and wherein the method further comprises translating the guest physical address to a host physical address.
 9. The method of claim 8, wherein the host physical address corresponds to an address of a partition executing under control of at least another level of virtualization, and wherein the method further comprises translating the host physical address to another host physical address.
 10. The method of claim 1, wherein at least one of the first type of address translation structure and the second type of address translation structure is selected from a set of translation types consisting of a hierarchical translation structure, a hash translation structure, and an offset translation structure. 